I am new to the MIPS world in general and the IDT chips in particular and
I wonder if someone who is familiar with them might be able to spare a few
minutes to help with understanding how this is supposed to work.
I have a board (a RouterBoard 532) which has one of these chips at its
heart and also has a Hynix 64Mb NAND flash chip on it. I have a patch
which patches things all over the place which adds support for the chip
to a 2.6.17-rc5 kernel, but I want to separate out just the support for
the NAND chip as a patch on its own. This patch successfully detects
the NAND chip when I load it onto the board.
When I take just the mods to the drivers/mtd/nand code and add them to
2.6.17 it is as though the NAND chip is never being selected, the manufacturer
and device id for the NAND chip come back as 0xff where with the rc5 patch
they come back as the correct values 0xad and 0x76 respectively.
Having read the IDT documentation I think that all this is controlled by
the Device Control Registers. The driver seems to expect that the chips is
accessed through DEV2, and in both cases when I boot the system up the values
in these registers are identical, and according to the IDT docs should cause
the chip select line to be raised.
I can not find anything else that controls the chip select lines, and I do
not have any hardware monitoring available to me (no oscilloscopes etc) to
try to see what is happening at the hardware level.
So my first question is whether my assumption that I only have to bother
myself with the DEV2 register is right, or is there another set of switches
that control the chip select lines?
Thanks in advance