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Re: [PATCH] fast path for rdhwr emulation for TLS

To: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Subject: Re: [PATCH] fast path for rdhwr emulation for TLS
From: Ralf Baechle <ralf@linux-mips.org>
Date: Fri, 7 Jul 2006 19:22:44 +0100
Cc: macro@linux-mips.org, linux-mips@linux-mips.org
In-reply-to: <20060708.014339.89274844.anemo@mba.ocn.ne.jp>
Original-recipient: rfc822;linux-mips@linux-mips.org
References: <20060708.000032.88471510.anemo@mba.ocn.ne.jp> <Pine.LNX.4.64N.0607071607520.25285@blysk.ds.pg.gda.pl> <20060708.011245.82794581.anemo@mba.ocn.ne.jp> <20060708.014339.89274844.anemo@mba.ocn.ne.jp>
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On Sat, Jul 08, 2006 at 01:43:39AM +0900, Atsushi Nemoto wrote:

> > >  For a VIVT I-cache this can result in a TLB exception.  TLB handlers are 
> > > not currently prepared for being called at the exception level.
> > 
> > Thanks, now I understand the problem.  Are there any good solutions?
> > Only I can think now is using handle_ri_slow for such CPUs.
> 
> Can we use Index_Load_Data_I to load the instruction code from icache?
> Just an idea...

In addition to what Maciej said - the format of instructions in the I-cache
is not necessarily the same as in memory.  Many processor store pre-decoded
instructions in the I-cache.

  Ralf

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