Re: [PATCH] fast path for rdhwr emulation for TLS

[Atsushi Nemoto <anemo@mba.ocn.ne.jp>]

On Sat, 08 Jul 2006 01:12:45 +0900 (JST), Atsushi Nemoto <anemo@mba.ocn.ne.jp> 
wrote:
> >  For a VIVT I-cache this can result in a TLB exception.  TLB handlers are 
> > not currently prepared for being called at the exception level.
> 
> Thanks, now I understand the problem.  Are there any good solutions?
> Only I can think now is using handle_ri_slow for such CPUs.

Can we use Index_Load_Data_I to load the instruction code from icache?
Just an idea...

---
Atsushi Nemoto