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[PATCH 2/2] vr41xx: define P4K bit for VR41xx

To: Ralf Baechle <ralf@linux-mips.org>
Subject: [PATCH 2/2] vr41xx: define P4K bit for VR41xx
From: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
Date: Sat, 8 Jul 2006 00:42:12 +0900
Cc: linux-mips <linux-mips@linux-mips.org>
Organization: TriPeaks Corporation
Original-recipient: rfc822;linux-mips@linux-mips.org
Sender: linux-mips-bounce@linux-mips.org
Hi Ralf,

This patch has defined P4K bit for VR41xx.
Please apply.

Yoichi

Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>

diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/mm/c-r4k.c 
mips/arch/mips/mm/c-r4k.c
--- mips-orig/arch/mips/mm/c-r4k.c      2006-07-06 18:03:06.162320750 +0900
+++ mips/arch/mips/mm/c-r4k.c   2006-07-06 18:03:13.127272250 +0900
@@ -862,7 +862,7 @@ static void __init probe_pcache(void)
                break;
 
        case CPU_VR4133:
-               write_c0_config(config & ~CONF_EB);
+               write_c0_config(config & ~VR41_CONF_P4K);
        case CPU_VR4131:
                /* Workaround for cache instruction bug of VR4131 */
                if (c->processor_id == 0x0c80U || c->processor_id == 0x0c81U ||
diff -pruN -X mips/Documentation/dontdiff mips-orig/include/asm-mips/mipsregs.h 
mips/include/asm-mips/mipsregs.h
--- mips-orig/include/asm-mips/mipsregs.h       2006-07-06 17:49:45.931927750 
+0900
+++ mips/include/asm-mips/mipsregs.h    2006-07-06 18:09:30.443242500 +0900
@@ -470,6 +470,7 @@
 
 /* Bits specific to the VR41xx.  */
 #define VR41_CONF_CS           (_ULCAST_(1) << 12)
+#define VR41_CONF_P4K          (_ULCAST_(1) << 13)
 #define VR41_CONF_BP           (_ULCAST_(1) << 16)
 #define VR41_CONF_M16          (_ULCAST_(1) << 20)
 #define VR41_CONF_AD           (_ULCAST_(1) << 23)

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