Adding special short path for emulationg RDHWR which is used to
support TLS.
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S
index b563811..545bcb1 100644
--- a/arch/mips/kernel/genex.S
+++ b/arch/mips/kernel/genex.S
@@ -357,7 +357,7 @@ #endif
BUILD_HANDLER ibe be cli silent /* #6 */
BUILD_HANDLER dbe be cli silent /* #7 */
BUILD_HANDLER bp bp sti silent /* #9 */
- BUILD_HANDLER ri ri sti silent /* #10 */
+ BUILD_HANDLER ri_slow ri sti silent /* #10 */
BUILD_HANDLER cpu cpu sti silent /* #11 */
BUILD_HANDLER ov ov sti silent /* #12 */
BUILD_HANDLER tr tr sti silent /* #13 */
@@ -369,6 +369,39 @@ #endif
BUILD_HANDLER dsp dsp sti silent /* #26 */
BUILD_HANDLER reserved reserved sti verbose /* others */
+ .align 5
+ LEAF(handle_ri)
+ .set push
+ .set noat
+ mfc0 k0, CP0_CAUSE
+ MFC0 k1, CP0_EPC
+ bltz k0, handle_ri_slow /* if delay slot */
+ lw k0, (k1)
+ li k1, 0x7c03e83b /* rdhwr v1,$29 */
+ bne k0, k1, handle_ri_slow /* if not ours */
+ get_saved_sp /* k1 := current_thread_info */
+ MFC0 k0, CP0_EPC
+ LONG_ADDIU k0, 4
+ .set noreorder
+#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
+ ori k1, _THREAD_MASK
+ xori k1, _THREAD_MASK
+ LONG_L v1, TI_TP_VALUE(k1)
+ jr k0
+ rfe
+#else
+ /* I hope three instructions between MTC0 and ERET are enough... */
+ MTC0 k0, CP0_EPC
+ ori k1, _THREAD_MASK
+ xori k1, _THREAD_MASK
+ LONG_L v1, TI_TP_VALUE(k1)
+ .set mips3
+ eret
+ .set mips0
+#endif
+ .set pop
+ END(handle_ri)
+
#ifdef CONFIG_64BIT
/* A temporary overflow handler used by check_daddi(). */
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