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Re: Problem with TLB mcheck!

To: linux-mips@linux-mips.org
Subject: Re: Problem with TLB mcheck!
From: art <art@sigrand.ru>
Date: Wed, 31 May 2006 18:02:34 +0700
Cc: macro@linux-mips.org, ralf@linux-mips.org, rongkai.zhan@windriver.com
Organization: Sigrand LLC
Original-recipient: rfc822;linux-mips@linux-mips.org
Reply-to: art <art@sigrand.ru>
Sender: linux-mips-bounce@linux-mips.org
Hello , All

I think I'm on wright way:
I change /arch/mips/mm/tlbex.c:

--- /home/artpol/router/buildroot/kernels/linux-2.6.16-old/arch/mips/mm/tlbex.c 
2006-03-20 11:35:39.000000000 +0000
+++ tlbex.c     2006-05-31 16:57:58.000000000 +0000
@@ -742,7 +742,7 @@
        }
 #endif

-       memcpy((void *)CAC_BASE, tlb_handler, 0x80);
+       memcpy((void *)ebase, tlb_handler, 0x80);
 }

 /*
@@ -838,6 +838,7 @@
                break;

        case CPU_R4300:
+       case CPU_4KC:
        case CPU_5KC:
        case CPU_TX49XX:
        case CPU_AU1000:
@@ -852,13 +853,12 @@

        case CPU_R10000:
        case CPU_R12000:
-       case CPU_4KC:
        case CPU_SB1:
        case CPU_SB1A:
        case CPU_4KSC:
        case CPU_20KC:
        case CPU_25KF:
-               tlbw(p);
+               tlbw(p);
                break;

        case CPU_NEVADA:
@@ -1260,7 +1260,7 @@
        }
 #endif

-       memcpy((void *)CAC_BASE, final_handler, 0x100);
+       memcpy((void *)ebase, final_handler, 0x100);
}

And it seem than no problem now (`cat /bin/busybox > box` work as much
as need!).
I think this is wright way, but not all - I'am not guru in memory
subsystem and can miss something! So wait for your advices!



-- 
Best regards,
 art                          mailto:art@sigrand.ru



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