Re: [PATCH] Save write-only Config.OD from being clobbered

[Sergei Shtylyov <sshtylyov@ru.mvista.com>]

Hello.

   Save the Config.OD bit from being clobbered by coherency_setup(). This
bit, when set, fixes various errata in the early steppings of Au1x00 SOCs.
Unfortunately, the bit was write-only on the most early of them. In addition,
also restore the bit after a wakeup from sleep.

WBR, Sergei

Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>

Index: linux-mips/arch/mips/au1000/common/sleeper.S
===================================================================
--- linux-mips.orig/arch/mips/au1000/common/sleeper.S
+++ linux-mips/arch/mips/au1000/common/sleeper.S
@@ -112,6 +112,11 @@ sdsleep:
        mtc0    k0, CP0_PAGEMASK
        lw      k0, 0x14(sp)
        mtc0    k0, CP0_CONFIG
+
+       /* We need to catch the ealry Alchemy SOCs with
+        * the write-only Config[OD] bit and set it back to one...
+        */
+       jal     au1x00_fixup_config_od
        lw      $1, PT_R1(sp)
        lw      $2, PT_R2(sp)
        lw      $3, PT_R3(sp)
Index: linux-mips/arch/mips/mm/c-r4k.c
===================================================================
--- linux-mips.orig/arch/mips/mm/c-r4k.c
+++ linux-mips/arch/mips/mm/c-r4k.c
@@ -1136,6 +1136,26 @@ static void __init setup_scache(void)
        c->options |= MIPS_CPU_SUBSET_CACHES;
 }
 
+void au1x00_fixup_config_od(void)
+{
+       /*
+        * c0_config.od (bit 19) was write only (and read as 0)
+        * on the early revisions of Alchemy SOCs.  It disables the bus
+        * transaction overlapping and needs to be set to fix various errata.
+        */
+       switch (current_cpu_data.cputype) {
+       case CPU_AU1000: /* rev. DA, HA, HB */
+       case CPU_AU1100: /* rev. AB, BA, BC ?? */
+               if ((read_c0_prid() & 0xff) < 3)
+                       set_c0_config(1 << 19);
+               break;
+       case CPU_AU1500: /* rev. AB */
+               if ((read_c0_prid() & 0xff) < 1)
+                       set_c0_config(1 << 19);
+               break;
+       }
+}
+
 static inline void coherency_setup(void)
 {
        change_c0_config(CONF_CM_CMASK, CONF_CM_DEFAULT);
@@ -1156,6 +1176,13 @@ static inline void coherency_setup(void)
        case CPU_R4400MC:
                clear_c0_config(CONF_CU);
                break;
+       default:
+               /*
+                * We need to catch the ealry Alchemy SOCs with
+                * the write-only co_config.od bit and set it back to one...
+                */
+               au1x00_fixup_config_od();
+               break;
        }
 }