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Re: Problem with TLB mcheck!

To: Ralf Baechle <ralf@linux-mips.org>
Subject: Re: Problem with TLB mcheck!
From: "Maciej W. Rozycki" <macro@linux-mips.org>
Date: Wed, 24 May 2006 17:29:45 +0100 (BST)
Cc: art <art@sigrand.ru>, linux-mips@linux-mips.org
In-reply-to: <20060524155207.GB25452@linux-mips.org>
Original-recipient: rfc822;linux-mips@linux-mips.org
References: <19691.060524@sigrand.ru> <Pine.LNX.4.64N.0605241304090.7887@blysk.ds.pg.gda.pl> <20060524144917.GA11657@linux-mips.org> <Pine.LNX.4.64N.0605241605120.7887@blysk.ds.pg.gda.pl> <20060524155207.GB25452@linux-mips.org>
Sender: linux-mips-bounce@linux-mips.org
On Wed, 24 May 2006, Ralf Baechle wrote:

> >  We have got PRId to filter out these.  Though rev. 2 of the architecture 
> > limits conditions when to raise the exception so it may eventually be a 
> > non-issue.
> 
> Doesn't really help, the exception is asynchronous by definition, so the
> CPU can be far away by the time it's struck be the lightning bolt.
> Machine check is just a _bad_ place to be.

 It does help -- while it is asynchronous indeed, TLB writes are far rarer 
than reads and happen in well defined places and a machine check will 
happen within limited time after such a write attempt, at the very worst.  
With the 4Kc the machine check looks synchronous.

  Maciej

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