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Re: Problem with TLB mcheck!

To: "Maciej W. Rozycki" <macro@linux-mips.org>
Subject: Re: Problem with TLB mcheck!
From: Ralf Baechle <ralf@linux-mips.org>
Date: Wed, 24 May 2006 16:52:07 +0100
Cc: art <art@sigrand.ru>, linux-mips@linux-mips.org
In-reply-to: <Pine.LNX.4.64N.0605241605120.7887@blysk.ds.pg.gda.pl>
Original-recipient: rfc822;linux-mips@linux-mips.org
References: <19691.060524@sigrand.ru> <Pine.LNX.4.64N.0605241304090.7887@blysk.ds.pg.gda.pl> <20060524144917.GA11657@linux-mips.org> <Pine.LNX.4.64N.0605241605120.7887@blysk.ds.pg.gda.pl>
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On Wed, May 24, 2006 at 04:11:12PM +0100, Maciej W. Rozycki wrote:

> > Depends on when exactly a CPU will raise the machine check.  On some cores
> > the information in registers is totally useless if not even missloading.
> 
>  We have got PRId to filter out these.  Though rev. 2 of the architecture 
> limits conditions when to raise the exception so it may eventually be a 
> non-issue.

Doesn't really help, the exception is asynchronous by definition, so the
CPU can be far away by the time it's struck be the lightning bolt.
Machine check is just a _bad_ place to be.

> > But generally a good idea, patch below.
> 
>  Except Index would be a bit more useful than HI. ;-)

Index may not matter at all in case of a TLBWR.  But yes, will include
index in the patch.

  Ralf

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