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Re: Problem with TLB mcheck!

To: Ralf Baechle <ralf@linux-mips.org>
Subject: Re: Problem with TLB mcheck!
From: "Maciej W. Rozycki" <macro@linux-mips.org>
Date: Wed, 24 May 2006 16:11:12 +0100 (BST)
Cc: art <art@sigrand.ru>, linux-mips@linux-mips.org
In-reply-to: <20060524144917.GA11657@linux-mips.org>
Original-recipient: rfc822;linux-mips@linux-mips.org
References: <19691.060524@sigrand.ru> <Pine.LNX.4.64N.0605241304090.7887@blysk.ds.pg.gda.pl> <20060524144917.GA11657@linux-mips.org>
Sender: linux-mips-bounce@linux-mips.org
On Wed, 24 May 2006, Ralf Baechle wrote:

> Depends on when exactly a CPU will raise the machine check.  On some cores
> the information in registers is totally useless if not even missloading.

 We have got PRId to filter out these.  Though rev. 2 of the architecture 
limits conditions when to raise the exception so it may eventually be a 
non-issue.

> But generally a good idea, patch below.

 Except Index would be a bit more useful than HI. ;-)

  Maciej

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