On Wed, May 24, 2006 at 01:45:26PM +0100, Maciej W. Rozycki wrote:
j The "linux-mips" mailing list (as cc-ed in this response) is a better
> place to ask such questions.
> You haven't included some important information, such as the version
> number of your Linux kernel and where you got your sources from. Without
> that bit all I can say is there is something wrong with handling of the
> Ralf, BTW -- shouldn't we report the Index, EntryHi and possibly EntryLo*
> registers in show_regs() if the cause is a machine check? I think it
> would be useful and these registers shouldn't have been corrupted since
> the triggering tlbw* instruction. A call to show_code() could be useful
> too, to determine which kind of TLB exception has been taken originally.
Depends on when exactly a CPU will raise the machine check. On some cores
the information in registers is totally useless if not even missloading.
But generally a good idea, patch below.
Signed-off-by: Ralf Baechle <email@example.com>
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 35cb08d..44a30e6 100644
@@ -819,8 +819,19 @@ asmlinkage void do_watch(struct pt_regs
asmlinkage void do_mcheck(struct pt_regs *regs)
+ const int field = 2 * sizeof(unsigned long);
+ printk("Hi : %0*lx\n", field, regs->hi);
+ printk("Pagemask: %0*x\n", read_c0_pagemask());
+ printk("EntryHi : %0*lx\n", field, read_c0_entryhi());
+ printk("EntryLo0: %0*lx\n", field, read_c0_entrylo0());
+ printk("EntryLo1: %0*lx\n", field, read_c0_entrylo1());
+ show_code((unsigned int *) regs->cp0_epc);
* Some chips may have other causes of machine check (e.g. SB1
* graduation timer)