Re: [PATCH] fix interrupt handling for R2 CPUs

linux-mips

Re: [PATCH] fix interrupt handling for R2 CPUs

To:	Ralf Baechle <ralf@linux-mips.org>
Subject:	Re: [PATCH] fix interrupt handling for R2 CPUs
From:	Thiemo Seufer <ths@networkno.de>
Date:	Tue, 16 May 2006 18:55:08 +0100
Cc:	linux-mips@linux-mips.org
In-reply-to:	<20060516174848.GA30064@linux-mips.org>
Original-recipient:	rfc822;linux-mips@linux-mips.org
References:	<20060515172747.GF9026@networkno.de> <20060516174848.GA30064@linux-mips.org>
Sender:	linux-mips-bounce@linux-mips.org
User-agent:	Mutt/1.5.11+cvs20060403

Ralf Baechle wrote:
> On Mon, May 15, 2006 at 06:27:47PM +0100, Thiemo Seufer wrote:
> 
> > a) only the low bit is used for status flags if CONFIG_CPU_MIPSR2,
> >    consistent with the use of di/ei.
> > 
> > b) the ERL/EXL bits get cleared as well.
> 
> Does this patch make a difference for you anywhere?

It fixes a MIPS32R2-compiled qemu kernel for me which broke when the
new bitfield instructions were added.


Thiemo

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