| To: | linux-mips@linux-mips.org |
|---|---|
| Subject: | [PATCH] fix interrupt handling for R2 CPUs |
| From: | Thiemo Seufer <ths@networkno.de> |
| Date: | Mon, 15 May 2006 18:27:47 +0100 |
| Cc: | ralf@linux-mips.org |
| Original-recipient: | rfc822;linux-mips@linux-mips.org |
| Sender: | linux-mips-bounce@linux-mips.org |
| User-agent: | Mutt/1.5.11+cvs20060403 |
This patch ensures that
a) only the low bit is used for status flags if CONFIG_CPU_MIPSR2,
consistent with the use of di/ei.
b) the ERL/EXL bits get cleared as well.
Signed-off-by: Thiemo Seufer <ths@networkno.de>
--- linux-orig/include/asm-mips/interrupt.h 2006-04-24 12:02:35.000000000
+0100
+++ linux-work/include/asm-mips/interrupt.h 2006-05-15 18:10:49.000000000
+0100
@@ -102,6 +102,9 @@ __asm__ (
" mfc0 \\flags, $2, 1 \n"
#else
" mfc0 \\flags, $12 \n"
+#ifdef CONFIG_CPU_MIPSR2
+ " andi \\flags, 1 \n"
+#endif
#endif
" .set pop \n"
" .endm \n");
@@ -169,7 +172,7 @@ __asm__ (
* Fast, dangerous. Life is fun, life is good.
*/
" mfc0 $1, $12 \n"
- " ins $1, \\flags, 0, 1 \n"
+ " ins $1, \\flags, 0, 5 \n"
" mtc0 $1, $12 \n"
#else
" mfc0 $1, $12 \n"
|
| <Prev in Thread] | Current Thread | [Next in Thread> |
|---|---|---|
| ||
| Previous by Date: | [PATCH] Update/Fix instruction definitions, Thiemo Seufer |
|---|---|
| Next by Date: | Re: [PATCH] Qemu system shutdown support, Martin Michlmayr |
| Previous by Thread: | [PATCH] Update/Fix instruction definitions, Thiemo Seufer |
| Next by Thread: | Re: [PATCH] fix interrupt handling for R2 CPUs, Ralf Baechle |
| Indexes: | [Date] [Thread] [Top] [All Lists] |