| To: | Atsushi Nemoto <anemo@mba.ocn.ne.jp> |
|---|---|
| Subject: | Re: Instruction error with cache opcode |
| From: | John Miller <jamiller1110@cox.net> |
| Date: | Sun, 14 May 2006 21:35:10 -0400 |
| Cc: | linux-mips@linux-mips.org |
| In-reply-to: | <20060515.100659.126574393.nemoto@toshiba-tops.co.jp> |
| Original-recipient: | rfc822;linux-mips@linux-mips.org |
| References: | <446735C6.2080306@mountolympos.net> <002a01c67761$253e97f0$0202a8c0@Ulysses> <4467796E.8060000@mountolympos.net> <20060515.100659.126574393.nemoto@toshiba-tops.co.jp> |
| Sender: | linux-mips-bounce@linux-mips.org |
| User-agent: | Thunderbird 1.5 (X11/20060313) |
Atsushi Nemoto wrote: That got it! Sorry, I had my head up somewhere it was not supposed to be. I do not know how many times I went over cacheops.h and missed the fact that Fill was defined, not Fill_I. One I changed my code to Fill, it built the kernel nicely. It still died before the first printk :) but at least I am a little closer. I got Fill_I out of the See MIPS Run book, it has the same option hex (0x14) as Fill, does anyone know why this changed?On Sun, 14 May 2006 14:39:42 -0400, John Miller <jamiller1110@cox.net> wrote:I included asm/cacheops.h from the kernel tree, it is defined there as : #define Index_Store_Tag_I 0x08Then how about Fill_I ? --- Atsushi Nemoto |
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