linux-mips
[Top] [All Lists]

Re: [PATCH 1/2] Wind River 4KC PPMC Eval Board Support

To: "Mark.Zhan" <rongkai.zhan@windriver.com>
Subject: Re: [PATCH 1/2] Wind River 4KC PPMC Eval Board Support
From: Ralf Baechle <ralf@linux-mips.org>
Date: Wed, 10 May 2006 16:32:16 +0100
Cc: linux-mips@linux-mips.org
In-reply-to: <446152CC.6020904@windriver.com>
Original-recipient: rfc822;linux-mips@linux-mips.org
References: <445C6694.6010901@windriver.com> <20060509164127.GA10647@linux-mips.org> <446152CC.6020904@windriver.com>
Sender: linux-mips-bounce@linux-mips.org
User-agent: Mutt/1.4.2.1i
On Wed, May 10, 2006 at 10:41:16AM +0800, Mark.Zhan wrote:

> After looking into the changeset ac58afdfac792c0583af30dbd9eae53e24c78b, 
>  I find what I want to do has been done by you:-)

I don't have this changeset in my tree; I assume you're refering to the
patch titled "[MIPS] Rewrite all the assembler interrupt handlers to C".

> For those MIPS32 boards which only use IRQ_CPU, I think, we can provide 
> a default plat_irq_dispatch() implemention, maybe like this:
> 
> asmlinkage plat_irq_dispatch(struct pt_regs *regs)
> {
>       unsigned int pending = read_c0_status() & read_c0_cause();
>       int irq;
> 
>       irq = ffs(pending >> 8) - 1;
>       return do_IRQ(irq, regs);
> }
> 
> I this it will clean up more codes......

There are only few such extremly simple platforms in the tree.  The purpose
of me rewriting all the handlers to assembler was that many of the handlers
has bugs that would not exist in a high level language and much of the code
was not scheduled very well - something which gcc does pretty well these
days.

  Ralf

<Prev in Thread] Current Thread [Next in Thread>