| To: | Bin Chen <binary.chen@gmail.com> |
|---|---|
| Subject: | Re: why not put 64 bit value directly to register |
| From: | Thiemo Seufer <ths@networkno.de> |
| Date: | Wed, 26 Apr 2006 12:28:09 +0100 |
| Cc: | linux-mips@linux-mips.org |
| In-reply-to: | <5800c1cc0604252149i55ab181ax7d9355a869a9b251@mail.gmail.com> |
| Original-recipient: | rfc822;linux-mips@linux-mips.org |
| References: | <5800c1cc0604252149i55ab181ax7d9355a869a9b251@mail.gmail.com> |
| Sender: | linux-mips-bounce@linux-mips.org |
| User-agent: | Mutt/1.5.11+cvs20060403 |
Bin Chen wrote:
> Hi,
>
> This code is snip from u-boot, I don't know why the 32bit-64bit conversion
> is needed, why not put val directly to register but do the transform?
>
> static void cvmx_write_cop0_entry_lo_0(uint64_t val)
> {
> uint32_t val_low = val & 0xffffffff;
> uint32_t val_high = val >> 32;
>
> uint32_t tmp; /* temp register */
>
> asm volatile (
> " .set mips64 \n"
> " .set noreorder \n"
> /* Standard twin 32 bit -> 64 bit construction */
> " dsll %[valh], 32 \n"
> " dla %[tmp], 0xffffffff \n"
> " and %[vall], %[tmp], %[vall] \n"
> " daddu %[valh], %[valh], %[vall] \n"
> /* Combined value is in valh */
> " dmtc0 %[valh],$2,0 \n"
> " .set reorder \n"
> :[tmp] "=&r" (tmp) : [valh] "r" (val_high), [vall] "r" (val_low) );
> }
This will convert on a 64bit capable MIPS CPU an o32 ABI register pair
holding a long long to a 64bit register value, and write that to a CP0
register.
It will break if an exception happens in between unless the exception
handlers save/restore the upper half as well.
Thiemo
|
| <Prev in Thread] | Current Thread | [Next in Thread> |
|---|---|---|
| ||
| Previous by Date: | Re: Reading an entire cacheline, Kevin D. Kissell |
|---|---|
| Next by Date: | Re: Crosstools for MALTA MIPS in little endian, Nigel Stephens |
| Previous by Thread: | why not put 64 bit value directly to register, Bin Chen |
| Next by Thread: | Problem with malta 4Kc on 2.6.16, Kishore K |
| Indexes: | [Date] [Thread] [Top] [All Lists] |