On Tue, Apr 18, 2006 at 10:50:28AM -0700, Raj Palani wrote:
> I have a question regarding the following warning in the
> What is the reason for this comment and in case it is not SMP safe, what
> are the changes needed to make it SMP safe?
> * Almost all MIPS CPUs define 8 interrupt sources. They are typically
> * level triggered (i.e., cannot be cleared from CPU; must be cleared from
> * device). The first two are software interrupts which we don't really
> * use or support. The last one is usually the CPU timer interrupt if
> * counter register is present or, for CPUs with an external FPU, by
> * convention it's the FPU exception interrupt.
> * Don't even think about using this on SMP. You have been warned.
> * This file exports one global function:
> * void mips_cpu_irq_init(int irq_base);
The interrupt controller is part of the processor itself, so any
manipulation of it's control registers needs to be done on the processor
itself. On an SMP system however calling enable_irq, disable_irq etc.
is legal on any CPU, so the wrong processor's interrupts might be
changed. Also there is no provision for interrupts that are handled the
same on all processor. The count / compare interrupt is a typical
example for this.
The answer is a little more complicated if considering multithreading a la
34K due to the more complicated priviledged resource architecture but the
underlying problem is the same.