Retain the write-only OD bit from being clobbered by coherency_setup().
PS: Looks like this patch is stuck uncommitted since December, while it's a
serious issue causing the kernel lockups.
Signed-off-by: Konstantin Baidarov <email@example.com>
Signed-off-by: Sergei Shtylyov <firstname.lastname@example.org>
diff --git a/arch/mips/au1000/common/setup.c b/arch/mips/au1000/common/setup.c
index 08c8c85..e36289b 100644
@@ -143,6 +143,17 @@ void __init plat_setup(void)
+ * Fix up write-only Config[OD] bit after a write to that register. Since the
+ * bit always reads as 0 on those SOC revs that require it to be set to fight
+ * the various errata, we need to set it back to 1...
+ if (cur_cpu_spec->cpu_od)
/* This routine should be valid for all Au1x based boards */
phys_t __fixup_bigphys_addr(phys_t phys_addr, phys_t size)
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 422b55f..8447699 100644
@@ -1201,8 +1201,20 @@ static void __init setup_scache(void)
static inline void coherency_setup(void)
+ extern void au1x00_fixup_config_od(void);
+ * c0_config.od (bit 19) is write only (and reads as 0) on many early
+ * revs of AMD Au1x00 SOCs. It disables the bus transaction overlapping
+ * and needs to be set to correct the various errata. So if it has been
+ * set by the board setup code we must leave it set...
* c0_status.cu=0 specifies that updates by the sc instruction use
* the coherency mode specified by the TLB; 1 means cachable