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Re: [PATCH] Retain the write-only OD from being clobbered

To: Linux MIPS <linux-mips@linux-mips.org>
Subject: Re: [PATCH] Retain the write-only OD from being clobbered
From: Sergei Shtylyov <sshtylyov@dev.rtsoft.ru>
Date: Fri, 24 Mar 2006 23:33:42 +0300
Cc: Jordan Crouse <jordan.crouse@amd.com>, ralf@linux-mips.org
In-reply-to: <43838957.2020106@ru.mvista.com>
Organization: RTSoft, Inc.
Original-recipient: rfc822;linux-mips@linux-mips.org
References: <20051122205938.GR18119@cosmic.amd.com> <43838957.2020106@ru.mvista.com>
Sender: linux-mips-bounce@linux-mips.org
User-agent: Mozilla/5.0 (X11; U; Linux i686; rv:1.7.2) Gecko/20040803
Hello.

    Retain the write-only OD bit from being clobbered by coherency_setup().

WBR, Sergei

PS: Looks like this patch is stuck uncommitted since December, while it's a
serious issue causing the kernel lockups.

Signed-off-by: Konstantin Baidarov <kbaidarov@ru.mvista.com>
Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>


diff --git a/arch/mips/au1000/common/setup.c b/arch/mips/au1000/common/setup.c
index 08c8c85..e36289b 100644
--- a/arch/mips/au1000/common/setup.c
+++ b/arch/mips/au1000/common/setup.c
@@ -143,6 +143,17 @@ void __init plat_setup(void)
        au_writel(0, SYS_TOYTRIM);
 }
 
+/*
+ * Fix up write-only Config[OD] bit after a write to that register. Since the
+ * bit always reads as 0 on those SOC revs that require it to be set to fight
+ * the various errata, we need to set it back to 1...
+ */
+void au1x00_fixup_config_od(void)
+{
+       if (cur_cpu_spec[0]->cpu_od)
+               set_c0_config(1<<19);
+}
+
 #if defined(CONFIG_64BIT_PHYS_ADDR)
 /* This routine should be valid for all Au1x based boards */
 phys_t __fixup_bigphys_addr(phys_t phys_addr, phys_t size)
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 422b55f..8447699 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -1201,8 +1201,20 @@ static void __init setup_scache(void)
 
 static inline void coherency_setup(void)
 {
+       extern void au1x00_fixup_config_od(void);
+
        change_c0_config(CONF_CM_CMASK, CONF_CM_DEFAULT);
 
+#ifdef CONFIG_SOC_AU1X00
+       /*
+        * c0_config.od (bit 19) is write only (and reads as 0) on many early
+        * revs of AMD Au1x00 SOCs. It disables the bus transaction overlapping
+        * and needs to be set to correct the various errata. So if it has been
+        * set by the board setup code we must leave it set...
+        */
+       au1x00_fixup_config_od();
+#endif
+
        /*
         * c0_status.cu=0 specifies that updates by the sc instruction use
         * the coherency mode specified by the TLB; 1 means cachable



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