| To: | zzh.hust@gmail.com |
|---|---|
| Subject: | Re: bogus packet in ei_receive of 8390.c |
| From: | Atsushi Nemoto <anemo@mba.ocn.ne.jp> |
| Date: | Mon, 27 Feb 2006 11:10:20 +0900 (JST) |
| Cc: | linux-mips@linux-mips.org |
| In-reply-to: | <50c9a2250602261729q543eb515hff7af85153ac779@mail.gmail.com> |
| Original-recipient: | rfc822;linux-mips@linux-mips.org |
| References: | <50c9a2250602251831n27d11b5ar7a309c9716a8683a@mail.gmail.com> <20060226.230541.75185772.anemo@mba.ocn.ne.jp> <50c9a2250602261729q543eb515hff7af85153ac779@mail.gmail.com> |
| Sender: | linux-mips-bounce@linux-mips.org |
>>>>> On Mon, 27 Feb 2006 09:29:23 +0800, zhuzhenhua <zzh.hust@gmail.com> said: zzh> our board is a FPGA board for embedded system, there is no ISA, zzh> and use memory map IO, is there anything need to configure? Even if it is not true ISA, your FPGA should drive ISA-like signals for the chip. AC timings of these signals should meet the requirements of the chip. I do not know they are configurable or not. Do cross-check the 8019 datasheet and the FPGA specification. zzh> now i printk the ISR and RSR value when bogus packet accepted, zzh> are these two registers correct? messages as follow It seems correct. So it would be something wrong with get_8390_hdr ... --- Atsushi Nemoto |
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