linux-mips
[Top] [All Lists]

Re: [PATCH] fix cache coherency issues

To: yoichi_yuasa@tripeaks.co.jp
Subject: Re: [PATCH] fix cache coherency issues
From: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Date: Tue, 14 Feb 2006 12:08:46 +0900 (JST)
Cc: linux-mips@linux-mips.org, ralf@linux-mips.org
In-reply-to: <20060214112653.25ed3e05.yoichi_yuasa@tripeaks.co.jp>
Original-recipient: rfc822;linux-mips@linux-mips.org
References: <20060214105928.0cd46e6f.yoichi_yuasa@tripeaks.co.jp> <20060214.111547.21591480.nemoto@toshiba-tops.co.jp> <20060214112653.25ed3e05.yoichi_yuasa@tripeaks.co.jp>
Sender: linux-mips-bounce@linux-mips.org
>>>>> On Tue, 14 Feb 2006 11:26:53 +0900, Yoichi Yuasa 
>>>>> <yoichi_yuasa@tripeaks.co.jp> said:
yuasa> Here is the boot log.

Thanks.  Could you try with this patch?

http://www.linux-mips.org/cgi-bin/mesg.cgi?a=linux-mips&i=20060204.015356.74753400.anemo%40mba.ocn.ne.jp

Or this quick workaround?

diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 1b71d91..5bd413f 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -425,7 +425,7 @@ static inline void local_r4k_flush_cache
         * Do indexed flush, too much work to get the (possible) TLB refills
         * to work correctly.
         */
-       addr = INDEX_BASE + (addr & (dcache_size - 1));
+       addr = INDEX_BASE + (addr & (current_cpu_data.dcache.waysize - 1));
        if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) {
                r4k_blast_dcache_page_indexed(addr);
                if (exec && !cpu_icache_snoops_remote_store)

<Prev in Thread] Current Thread [Next in Thread>