| To: | Sergei Shtylylov <sshtylyov@ru.mvista.com> |
|---|---|
| Subject: | Re: [PATCH] TX49 MFC0 bug workaround |
| From: | Ralf Baechle <ralf@linux-mips.org> |
| Date: | Thu, 2 Feb 2006 22:11:32 +0000 |
| Cc: | Atsushi Nemoto <anemo@mba.ocn.ne.jp>, linux-mips@linux-mips.org |
| In-reply-to: | <43E25381.4060309@ru.mvista.com> |
| Original-recipient: | rfc822;linux-mips@linux-mips.org |
| References: | <20060203.013401.41198517.anemo@mba.ocn.ne.jp> <43E25381.4060309@ru.mvista.com> |
| Sender: | linux-mips-bounce@linux-mips.org |
| User-agent: | Mutt/1.4.2.1i |
On Thu, Feb 02, 2006 at 09:46:25PM +0300, Sergei Shtylylov wrote: > Atsushi Nemoto wrote: > >If mfc0 $12 follows store and the mfc0 is last instruction of a > >page and fetching the next instruction causes TLB miss, the result > >of the mfc0 might wrongly contain EXL bit. > > Hmm, a TLB miss in fetching from KSEG0?! It'll hit loadable modules which run in the mapped KSEG2/3 spaces. Ralf |
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