| To: | Atsushi Nemoto <anemo@mba.ocn.ne.jp> |
|---|---|
| Subject: | Re: [PATCH] TX49 MFC0 bug workaround |
| From: | "Maciej W. Rozycki" <macro@linux-mips.org> |
| Date: | Fri, 3 Feb 2006 10:17:58 +0000 (GMT) |
| Cc: | ralf@linux-mips.org, linux-mips@linux-mips.org |
| In-reply-to: | <20060203.111012.130238823.nemoto@toshiba-tops.co.jp> |
| Original-recipient: | rfc822;linux-mips@linux-mips.org |
| References: | <20060202165656.GC17352@linux-mips.org> <20060203.020428.59032357.anemo@mba.ocn.ne.jp> <20060202172434.GE17352@linux-mips.org> <20060203.111012.130238823.nemoto@toshiba-tops.co.jp> |
| Sender: | linux-mips-bounce@linux-mips.org |
On Fri, 3 Feb 2006, Atsushi Nemoto wrote: > It should be OK for all CPU while STI/CLI/KMODE macro always clear > bit[4:1] of status register. Could you confirm, Maciej ? Well, as long as RESTORE_SOME in <asm/stackframe.h> correctly restores the IEc, KUc, IEp and KUp bits in the status register this change should be OK for R3k-class processors. Maciej |
| Previous by Date: | Re: [patch 14/44] generic hweight{64,32,16,8}(), Ulrich Eckhardt |
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