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Re: [PATCH] TX49 MFC0 bug workaround

To: sshtylyov@ru.mvista.com
Subject: Re: [PATCH] TX49 MFC0 bug workaround
From: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Date: Fri, 03 Feb 2006 11:50:07 +0900 (JST)
Cc: ralf@linux-mips.org, macro@linux-mips.org, linux-mips@linux-mips.org
In-reply-to: <43E2BF68.2000208@ru.mvista.com>
Original-recipient: rfc822;linux-mips@linux-mips.org
References: <Pine.LNX.4.64N.0602021636380.11727@blysk.ds.pg.gda.pl> <20060202165656.GC17352@linux-mips.org> <43E2BF68.2000208@ru.mvista.com>
Sender: linux-mips-bounce@linux-mips.org
>>>>> On Fri, 03 Feb 2006 05:26:48 +0300, Sergei Shtylylov 
>>>>> <sshtylyov@ru.mvista.com> said:
sshtylyov>     And.. how do you imagine placing a NOP (which surely
sshtylyov> just moves MFC0 down so that it's a 1st insn. on the next
sshtylyov> page). What if it'll move it to the errata prone address
sshtylyov> from a safe one instead?

The NOP will break the "If mfc0 $12 follows store" condition.

Actually, the condition is more strict.  This is a code sequence from
the errata. (It seems English version is not updated yet...)

        Load/Store instruction
        Load/Store/Sync instruction
        Mfc0 rt,rd      ; rd is Status/Cause
        -- page boundary --
        nop             ; TLB mapped area

For Cause register case, Linux modules should never read it so it
would not be a problem.

---
Atsushi Nemoto

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