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Re: [PATCH] TX49 MFC0 bug workaround

To: sshtylyov@ru.mvista.com
Subject: Re: [PATCH] TX49 MFC0 bug workaround
From: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Date: Fri, 03 Feb 2006 10:17:05 +0900 (JST)
Cc: linux-mips@linux-mips.org, ralf@linux-mips.org
In-reply-to: <43E25381.4060309@ru.mvista.com>
Original-recipient: rfc822;linux-mips@linux-mips.org
References: <20060203.013401.41198517.anemo@mba.ocn.ne.jp> <43E25381.4060309@ru.mvista.com>
Sender: linux-mips-bounce@linux-mips.org
>>>>> On Thu, 02 Feb 2006 21:46:25 +0300, Sergei Shtylylov 
>>>>> <sshtylyov@ru.mvista.com> said:
>> If mfc0 $12 follows store and the mfc0 is last instruction of a
>> page and fetching the next instruction causes TLB miss, the result
>> of the mfc0 might wrongly contain EXL bit.

sshtylyov>     Hmm, a TLB miss in fetching from KSEG0?!

We can call these inline functions from modules running on KSEG2.

---
Atsushi Nemoto

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