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Re: [PATCH] TX49 MFC0 bug workaround

To: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Subject: Re: [PATCH] TX49 MFC0 bug workaround
From: Sergei Shtylylov <sshtylyov@ru.mvista.com>
Date: Thu, 02 Feb 2006 21:46:25 +0300
Cc: linux-mips@linux-mips.org, ralf@linux-mips.org
In-reply-to: <20060203.013401.41198517.anemo@mba.ocn.ne.jp>
Organization: MontaVista Software Inc.
Original-recipient: rfc822;linux-mips@linux-mips.org
References: <20060203.013401.41198517.anemo@mba.ocn.ne.jp>
Sender: linux-mips-bounce@linux-mips.org
User-agent: Mozilla/5.0 (X11; U; Linux i686; rv:1.7.2) Gecko/20040803
Hello.

Atsushi Nemoto wrote:
If mfc0 $12 follows store and the mfc0 is last instruction of a
page and fetching the next instruction causes TLB miss, the result
of the mfc0 might wrongly contain EXL bit.

   Hmm, a TLB miss in fetching from KSEG0?!

ERT-TX49H2-027, ERT-TX49H3-012, ERT-TX49HL3-006, ERT-TX49H4-008

Workaround: mask EXL bit of the result or place a nop before mfc0.

   Is this workaround really needed?

Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>

WBR, Sergei

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