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Re: [PATCH] TX49 MFC0 bug workaround

To: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Subject: Re: [PATCH] TX49 MFC0 bug workaround
From: Ralf Baechle <ralf@linux-mips.org>
Date: Thu, 2 Feb 2006 16:46:52 +0000
Cc: linux-mips@linux-mips.org
In-reply-to: <20060203.013401.41198517.anemo@mba.ocn.ne.jp>
Original-recipient: rfc822;linux-mips@linux-mips.org
References: <20060203.013401.41198517.anemo@mba.ocn.ne.jp>
Sender: linux-mips-bounce@linux-mips.org
User-agent: Mutt/1.4.2.1i
On Fri, Feb 03, 2006 at 01:34:01AM +0900, Atsushi Nemoto wrote:

> If mfc0 $12 follows store and the mfc0 is last instruction of a
> page and fetching the next instruction causes TLB miss, the result
> of the mfc0 might wrongly contain EXL bit.
> 
> ERT-TX49H2-027, ERT-TX49H3-012, ERT-TX49HL3-006, ERT-TX49H4-008
> 
> Workaround: mask EXL bit of the result or place a nop before mfc0.

Applied,

  Ralf

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