Sory it just pushed my hands mistakenly before I had competed it. Which
functionality provided with which CPLD register may be wrong. Valids both
the below one and the others.
Au1200 PCMCIA normally supports one chip. CPLD makes it available two chip.
On Friday 20 January 2006 16:59, firstname.lastname@example.org wrote:
> > The DBAu1200 evaluation board from AMD use the Xilinx's CPLD,
> > and Ethernet, IDE, BCSR... address line comes out from it.
> > BCSR(Board Configuration & Status Register) in CPLD have many
> > function like Enable/Disable the Interrupt and else.
> > I don't understand exactly why they are used and what they do in the
> > system.
> I didnt do much examination just some hours but let me say what I
> BCSR mainly involves with board elements like rotary switch, leds etc.
> It also provides master/slave PCMCIA. As for IDE, it provides DMA
> capability to the board. Normally Au1200 only supports PIO modes.
> The other CPLD, XCS128(CNTL_CPLD) seemed to me that it is a signal
> distribution center. For example, CS is connected to IDE, SMSC and
> daughter card interface. Which one to be signals routed is decided by
> CNTL. Maybe all the chip selects are rerouted by this CPLD. So all the
> buffers(SN74...) I am neither a board designer or know electronics much
> but they are used for consistent signal routing. These are just 2 my
> They are coupled. It is needed a new design to eliminate some
> > I just wonder if I don't use this and connect the IDE interface to the
> > static bus of Au1200 directly, I am not sure it is working well or
> > not.
> In a new design I dont see any reason why not to be provided that you
> can only use PIO modes.
> Bora SAHIN