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Re: [PATCH Cobalt 1/1] 64-bit fix

To: Ralf Baechle <ralf@linux-mips.org>
Subject: Re: [PATCH Cobalt 1/1] 64-bit fix
From: Jim Gifford <maillist@jg555.com>
Date: Tue, 17 Jan 2006 09:09:18 -0800
Cc: Martin Michlmayr <tbm@cyrius.com>, Peter Horton <pdh@colonel-panic.org>, linux-mips@linux-mips.org
In-reply-to: <20060117135145.GE3336@linux-mips.org>
Original-recipient: rfc822;linux-mips@linux-mips.org
References: <20050414185949.GA5578@skeleton-jack> <20060116154543.GA26771@deprecation.cyrius.com> <43CBCAAE.6030403@jg555.com> <20060117135145.GE3336@linux-mips.org>
Sender: linux-mips-bounce@linux-mips.org
User-agent: Thunderbird 1.5 (Windows/20051201)
As per our conversation Ralf, here is the patch without the iomap stuff in it.



--
----
Jim Gifford
maillist@jg555.com

Submitted By: Jim Gifford (patches at jg555 dot com)
Date: 2006-01-09
Initial Package Version: 2.6.15
Origin: Jim Gifford
Upstream Status: Not Accepted
Description: Various Fixes for MIPS architectures

diff -Naur linux-2.6.15.orig/include/asm-mips/addrspace.h 
linux-2.6.15/include/asm-mips/addrspace.h
--- linux-2.6.15.orig/include/asm-mips/addrspace.h      2006-01-03 
03:21:10.000000000 +0000
+++ linux-2.6.15/include/asm-mips/addrspace.h   2006-01-09 20:47:10.000000000 
+0000
@@ -124,7 +124,7 @@
 #define PHYS_TO_XKSEG_CACHED(p)                
PHYS_TO_XKPHYS(K_CALG_COH_SHAREABLE,(p))
 #define XKPHYS_TO_PHYS(p)              ((p) & TO_PHYS_MASK)
 #define PHYS_TO_XKPHYS(cm,a)           (_LLCONST_(0x8000000000000000) | \
-                                        ((cm)<<59) | (a))
+                                        ((unsigned long)(cm)<<59) | (a))
 
 #if defined (CONFIG_CPU_R4300)                                         \
     || defined (CONFIG_CPU_R4X00)                                      \
diff -Naur linux-2.6.15.orig/include/asm-mips/cobalt/cpu-feature-overrides.h 
linux-2.6.15/include/asm-mips/cobalt/cpu-feature-overrides.h
--- linux-2.6.15.orig/include/asm-mips/cobalt/cpu-feature-overrides.h   
1970-01-01 00:00:00.000000000 +0000
+++ linux-2.6.15/include/asm-mips/cobalt/cpu-feature-overrides.h        
2006-01-09 20:52:18.000000000 +0000
@@ -0,0 +1,17 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2006 Ralf Baechle
+ */
+#ifndef __ASM_COBALT_CPU_FEATURE_OVERRIDES_H
+#define __ASM_COBALT_CPU_FEATURE_OVERRIDES_H
+
+#ifdef CONFIG_64BIT
+#define cpu_has_llsc            0
+#else
+#define cpu_has_llsc            1
+#endif
+
+#endif /* __ASM_COBALT_CPU_FEATURE_OVERRIDES_H */
diff -Naur linux-2.6.15.orig/include/asm-mips/cobalt/ide.h 
linux-2.6.15/include/asm-mips/cobalt/ide.h
--- linux-2.6.15.orig/include/asm-mips/cobalt/ide.h     1970-01-01 
00:00:00.000000000 +0000
+++ linux-2.6.15/include/asm-mips/cobalt/ide.h  2006-01-09 20:47:10.000000000 
+0000
@@ -0,0 +1,83 @@
+
+/*
+ * PIO "in" transfers can cause D-cache lines to be allocated
+ * to the data being read. If the target is the page cache then
+ * the kernel can create a user space mapping of the same page
+ * without flushing it from the D-cache. This has large potential
+ * to create cache aliases. The Cobalts seem to trigger this
+ * problem easily.
+ *
+ * MIPs doesn't have a flush_dcache_range() so we roll
+ * our own.
+ *
+ * -- pdh
+ */
+
+#define MAX_HWIFS                      2
+
+#include <asm/r4kcache.h>
+
+static inline void __flush_dcache(void)
+{
+       unsigned long dc_size, dc_line, addr, end;
+
+       dc_size = current_cpu_data.dcache.ways << 
current_cpu_data.dcache.waybit;
+       dc_line = current_cpu_data.dcache.linesz;
+
+       addr = CKSEG0;
+       end = addr + dc_size;
+
+       for (; addr < end; addr += dc_line)
+               flush_dcache_line_indexed(addr);
+}
+
+static inline void __flush_dcache_range(unsigned long start, unsigned long end)
+{
+       unsigned long dc_size, dc_line, addr;
+
+       dc_size = current_cpu_data.dcache.ways << 
current_cpu_data.dcache.waybit;
+       dc_line = current_cpu_data.dcache.linesz;
+
+       addr = start & ~(dc_line - 1);
+       end += dc_line - 1;
+
+       if (end - addr < dc_size)
+               for (; addr < end; addr += dc_line)
+                       flush_dcache_line(addr);
+       else
+               __flush_dcache();
+}
+
+static inline void __ide_insw(unsigned long port, void *addr, unsigned int 
count)
+{
+       insw(port, addr, count);
+
+       __flush_dcache_range((unsigned long) addr, (unsigned long) addr + count 
* 2);
+}
+
+static inline void __ide_insl(unsigned long port, void *addr, unsigned int 
count)
+{
+       insl(port, addr, count);
+
+       __flush_dcache_range((unsigned long) addr, (unsigned long) addr + count 
* 4);
+}
+
+static inline void __ide_mm_insw(volatile void __iomem *port, void *addr, 
unsigned int count)
+{
+       readsw(port, addr, count);
+
+       __flush_dcache_range((unsigned long) addr, (unsigned long) addr + count 
* 2);
+}
+
+static inline void __ide_mm_insl(volatile void __iomem *port, void *addr, 
unsigned int count)
+{
+       readsl(port, addr, count);
+
+       __flush_dcache_range((unsigned long) addr, (unsigned long) addr + count 
* 4);
+}
+
+#define insw                   __ide_insw
+#define insl                   __ide_insl
+
+#define __ide_mm_outsw         writesw
+#define __ide_mm_outsl         writesl
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