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Re: [PATCH Cobalt 1/1] 64-bit fix

To: Martin Michlmayr <tbm@cyrius.com>
Subject: Re: [PATCH Cobalt 1/1] 64-bit fix
From: Ralf Baechle <ralf@linux-mips.org>
Date: Tue, 17 Jan 2006 13:29:31 +0000
Cc: Peter Horton <pdh@colonel-panic.org>, linux-mips@linux-mips.org
In-reply-to: <20060116154543.GA26771@deprecation.cyrius.com>
Original-recipient: rfc822;linux-mips@linux-mips.org
References: <20050414185949.GA5578@skeleton-jack> <20060116154543.GA26771@deprecation.cyrius.com>
Sender: linux-mips-bounce@linux-mips.org
User-agent: Mutt/1.4.2.1i
On Mon, Jan 16, 2006 at 03:45:43PM +0000, Martin Michlmayr wrote:

> * Peter Horton <pdh@colonel-panic.org> [2005-04-14 19:59]:
> > This patch adds detection of broken 64-bit mode LL/SC on Cobalt units.
> > With this patch my Qube2700 boots a 64-bit build fine. The later units
> > have some problems with the Tulip driver.
> 
> Ralf, is this patch appropriate?  Can you please apply it or provide
> some feedback.

Runtime testing for that bug is fairly expensive as it adds a branch to
every instance of every type of atomic operation.  So we really want
cpu_has_llsc to be a constant so the compiler can optimize that.

So I suggest something like this in cpu-feature-overrides.h:

[...]
/*
 * R5000 has an interesting "restriction":  ll(d)/sc(d)
 * instructions to XKPHYS region simply do uncached bus
 * requests. This breaks all the atomic bitops functions.
 * so, for 64bit IP32 kernel we just don't use ll/sc.
 * This does not affect luserland.
 */
#ifdef CONFIG_64BIT
#define cpu_has_llsc            0
#else
#define cpu_has_llsc            1
#endif
[...]

The probe would upset the IP27 cache coherency logic and crash them btw.

  Ralf

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