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Re: [processor frequency]

To: "Mitchell, Earl" <earlm@mips.com>
Subject: Re: [processor frequency]
From: Wolfgang Denk <wd@denx.de>
Date: Tue, 10 Jan 2006 00:05:55 +0100
Cc: "Kevin D. Kissell" <kevink@mips.com>, "Sathesh Babu Edara" <satheshbabu.edara@analog.com>, linux-mips@linux-mips.org
In-reply-to: Your message of "Mon, 09 Jan 2006 14:00:50 PST." <3CB54817FDF733459B230DD27C690CEC010495E3@Exchange.MIPS.COM>
Original-recipient: rfc822;linux-mips@linux-mips.org
Sender: linux-mips-bounce@linux-mips.org
Hello,

in message <3CB54817FDF733459B230DD27C690CEC010495E3@Exchange.MIPS.COM> you 
wrote:
> 
> The desktop/server guys typically use much larger caches (i.e. >= 512K)
> and most have L2, compared to embedded systems which typically use less
> without an L2. So I'd also expect embedded guys using small caches to see 
> larger decreases in performance due to more cache misses (i.e. more 
> interrupts produce more evictions). 

Corrent. FYI: the system used in my tests is a PowerPC at 50 MHz  CPU
clock with 4 kB I-Cache and 4 kB D-Cache ...

Best regards,

Wolfgang Denk

-- 
Software Engineering:  Embedded and Realtime Systems,  Embedded Linux
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de
Every program has at least one bug and can be shortened by  at  least
one instruction - from which, by induction, one can deduce that every
program can be reduced to one instruction which doesn't work.

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