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Re: LL and SC instruction simulation

To: Sathesh Babu Edara <satheshbabu.edara@analog.com>
Subject: Re: LL and SC instruction simulation
From: Ralf Baechle <ralf@linux-mips.org>
Date: Mon, 9 Jan 2006 14:54:25 +0000
Cc: linux-mips-bounce@linux-mips.org, linux-mips@linux-mips.org
In-reply-to: <200601090749.k097nFaZ017891@lilac.hdcindia.analog.com>
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References: <200601090742.k097gYaZ017304@lilac.hdcindia.analog.com> <200601090749.k097nFaZ017891@lilac.hdcindia.analog.com>
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On Mon, Jan 09, 2006 at 01:19:46PM +0530, Sathesh Babu Edara wrote:

>    We have ported linux-2.4.18 and linux-2-6.12 kernel (mips.org)onto MIPS
> processor (CPU type lx4189).
> 
>  We observed that on 2.4 kernel,ll and sc instruction exception handlers
> hitting very often.
> Where as on linux-2.6.12 this is not happening.

> Can anybody have idea why this instructions are hitting on 2.4.18 kernel and
> not on 2-6.12 kernel.

Only ll/sc instructions in application software can be emulated, so it
would seem your application is behaving different on 2.4 and 2.6 kernels.

> What is the significance of these instructions?.

All sorts of atomic operations.  I suggest you read up on them in See MIPS
Run or short of that in the MIPS32/64 specification.

  Ralf

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