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Re: Kernel freezes in r4k_flush_icache_range() with CONFIG_CPU_MIPS32_R2

To: Maxime Bizon <mbizon@freebox.fr>
Subject: Re: Kernel freezes in r4k_flush_icache_range() with CONFIG_CPU_MIPS32_R2
From: Ralf Baechle <ralf@linux-mips.org>
Date: Thu, 22 Dec 2005 12:10:23 +0100
Cc: "Maciej W. Rozycki" <macro@linux-mips.org>, linux-mips@linux-mips.org
In-reply-to: <1135218691.9874.186.camel@sakura.staff.proxad.net>
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On Thu, Dec 22, 2005 at 03:31:31AM +0100, Maxime Bizon wrote:

> >  FYI, GCC 3.4.4 produces the following code which is clearly wrong:
> 
> > Please file a bug report at: "http://gcc.gnu.org/bugzilla/";.
> 
> Same with 3.3 and 3.2...
> 
> I'm really not familiar with inline assembly so I would appreciate that
> any gcc guru here confirm instruction_hazard() code is correct before I
> (or he) submit the bug report.
> 
> As the bug seems to be in all gcc versions, I guess we should find a
> workaround... I changed the code to use an asm label instead of the C
> label and the bug disappeared. But I'm not sure my changes are correct
> for any platform other than mine...

We ran into similar problems in the past.  It only seems to be a matter
of the code nearby and the exact options to trigger it.

The alternative is manually loading the address using la / dla which
defeats gcc's splitting of address loading.  And having to use different
code for 32-bit and 64-bit sucks.

> Could anyone with the right skills help me to write a valid workaround
> please ?
> 
> Here is what I have:
> 
> __asm__ __volatile__(
>         "lui $2,1f\n"
>         "addiu $2,1f\n"
>         "jr.hb $2\n1:":: );

Wrong, breaks 64-bit and uses $2 without telling gcc about it.

  Ralf

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