By multiple buses do you mean physical buses off of the CPU/companion chip or
one PCI bus then a bridge chip then next PCI Bus, and so on..
If it is the latter, then the code should be able to automatically take care of
it. The boot code should have already scanned the bus and annotated all of the
buses. The basic procedure is to start at bus 0, find the first bridge, look
past this bridge, find next one, until you find the last bridge. At this point
you backtrack and setup each bridge (primary, secondary #'s, etc.). Thne you
go out and do config cycles to find out what devices are available and map them
into the address space. When Linux comes up it should do something similar,
minus the setup to find out how many buses it has, and then how many devices it
has. The difference would be if linux finds a device it just reads the BARs to
find out where it is mapped.
If it is the former, then this should be a chip specific operation where Linux
would scan again but needs to know to scan on multiple interfaces/PCI buses.
The boot code should also be aware of this situation and map things
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[mailto:email@example.com]On Behalf Of Scott Ashcroft
Sent: Wednesday, December 07, 2005 12:46 PM
To: Mark Mason
Cc: Scott Ashcroft; firstname.lastname@example.org
Subject: Re: pci_iomap issues?
--- Mark Mason <email@example.com> wrote:
> Any system based on BCM1480s could have multiple pci
> busses (one PCI-X
> directly, and additional busses through HT/PCI-X
> bridges). For the
> BCM91480B board, we had to turn on PCI_DOMAINS to
> get this to work
I understand that there are machines with multiple PCI
busses out there but comparing the ppc64 code with the
proposed mips patches I don't see much difference.
Are the ppc64 people just breaking multiple PCI bus
machines, did something happen in the generic PCI code
which fixed the issue or is there just a difference I