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Au1550 system bus masters issue

To: <linux-mips@linux-mips.org>
Subject: Au1550 system bus masters issue
From: "David Sanchez" <david.sanchez@lexbox.fr>
Date: Mon, 5 Dec 2005 09:18:50 +0100
Original-recipient: rfc822;linux-mips@linux-mips.org
Sender: linux-mips-bounce@linux-mips.org
Thread-index: AcX5dIW+i6XFajUZSkKtR8AR8cRveQ==
Thread-topic: Au1550 system bus masters issue
Hi,

I notice the following issue in the specification update (v31420) of the
au1550:

"System bus masters (USB host, PCI, MAC0, MAC1, DDMA) may receive stale
data.

Description
-----------
System bus masters (USB host controller, PCI controller, MAC0, MAC1,
DDMA controller), when performing
coherent reads, may incorrectly receive stale data from memory instead
of valid modified data from the Au1
data cache. If the request for data arrives within a 3-clock window
prior to the cache line castout to memory,
the cache snoop response is incorrect and stale data is retrieved from
memory instead of the correct data from
the cache. The cache line castout then completes, and memory is updated.
Cache/memory data is not corrupted, but the specific bus read in not
valid.

Affected Step
-------------
AA

Workaround
----------
Do not enable cacheable master reads if the core modifies data in cache.

Status
------
Not Fixed"

Does somebody known if the linux kernel 2.6.10 integrates this
workaround ?

Thanks



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