I notice the following issue in the specification update (v31420) of the
"System bus masters (USB host, PCI, MAC0, MAC1, DDMA) may receive stale
System bus masters (USB host controller, PCI controller, MAC0, MAC1,
DDMA controller), when performing
coherent reads, may incorrectly receive stale data from memory instead
of valid modified data from the Au1
data cache. If the request for data arrives within a 3-clock window
prior to the cache line castout to memory,
the cache snoop response is incorrect and stale data is retrieved from
memory instead of the correct data from
the cache. The cache line castout then completes, and memory is updated.
Cache/memory data is not corrupted, but the specific bus read in not
Do not enable cacheable master reads if the core modifies data in cache.
Does somebody known if the linux kernel 2.6.10 integrates this