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[PATCH] Retain the write-only OD from being clobbered

To: linux-mips@linux-mips.org
Subject: [PATCH] Retain the write-only OD from being clobbered
From: "Jordan Crouse" <jordan.crouse@amd.com>
Date: Tue, 22 Nov 2005 13:59:38 -0700
Cc: ralf@linux-mips.org
Original-recipient: rfc822;linux-mips@linux-mips.org
Sender: linux-mips-bounce@linux-mips.org
User-agent: Mutt/1.5.11
First of several patches forwarded to me by Sergei Shtylyov.  Ralf,
these should be good to go for the tree.

Retain the write-only OD bit from being clobbered by coherency_setup()

Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>
---

 arch/mips/mm/c-r4k.c |   14 ++++++++++++++
 1 files changed, 14 insertions(+), 0 deletions(-)

diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 38223b4..044c468 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -29,6 +29,10 @@
 #include <asm/war.h>
 #include <asm/cacheflush.h> /* for run_uncached() */
 
+#ifdef CONFIG_SOC_AU1X00
+#include <au1000.h>
+#endif
+
 /*
  * Must die.
  */
@@ -1203,6 +1207,16 @@ static inline void coherency_setup(void)
 {
        change_c0_config(CONF_CM_CMASK, CONF_CM_DEFAULT);
 
+#ifdef CONFIG_SOC_AU1X00
+       /*
+        * c0_config.od (bit 19) is write only (and reads as 0) on many early
+        * revs of AMD Au1x00 SOCs. It disables the bus transaction overlapping 
+        * and needs to be set to correct the various errata. So if it has been
+        * set by the board setup code we must leave it set...
+        */
+       if (cur_cpu_spec[0]->cpu_od)
+               set_c0_config(1 << 19);
+#endif
        /*
         * c0_status.cu=0 specifies that updates by the sc instruction use
         * the coherency mode specified by the TLB; 1 means cachable


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