| To: | ralf@linux-mips.org |
|---|---|
| Subject: | Re: cpu_idle and cpu_wait |
| From: | Atsushi Nemoto <anemo@mba.ocn.ne.jp> |
| Date: | Thu, 17 Nov 2005 16:08:33 +0900 (JST) |
| Cc: | linux-mips@linux-mips.org |
| In-reply-to: | <20051117.112144.108306652.nemoto@toshiba-tops.co.jp> |
| Original-recipient: | rfc822;linux-mips@linux-mips.org |
| References: | <20051117.011906.25910026.anemo@mba.ocn.ne.jp> <20051116184201.GJ3229@linux-mips.org> <20051117.112144.108306652.nemoto@toshiba-tops.co.jp> |
| Sender: | linux-mips-bounce@linux-mips.org |
>>>>> On Thu, 17 Nov 2005 11:21:45 +0900 (JST), Atsushi Nemoto >>>>> <anemo@mba.ocn.ne.jp> said: anemo> And I checked x86 implemetation and found that HLT or MWAIT anemo> instruction also must be used with interrupts enabled. So IIUC anemo> it seems x86 have same latency problem too. No, I was wrong. MWAIT (and MONITOR) instruction provides something like "test and wait" mechanism. mwait_idle() is using them for thread_flag, so there is no latency problem on processors which have MWAIT/MONITOR. --- Atsushi Nemoto |
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