>>>>> On Wed, 16 Nov 2005 18:42:01 +0000, Ralf Baechle <email@example.com>
>> The CPU can surely exit from the WAIT instruction by interrupt even
>> if interrupts disabled?
ralf> That's implementation dependent behaviour, unfortunately.
I checked some MIPS32/MIPS64 datasheets and found that's really
inplementation-dependent. The answer is YES on (perhaps) all MIPS4K?
processors but NO on 20Kc, 24K ...
And I checked x86 implemetation and found that HLT or MWAIT
instruction also must be used with interrupts enabled. So IIUC it
seems x86 have same latency problem too.