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Re: cpu_idle and cpu_wait

To: ralf@linux-mips.org
Subject: Re: cpu_idle and cpu_wait
From: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Date: Thu, 17 Nov 2005 11:21:45 +0900 (JST)
Cc: linux-mips@linux-mips.org
In-reply-to: <20051116184201.GJ3229@linux-mips.org>
Original-recipient: rfc822;linux-mips@linux-mips.org
References: <20051117.011906.25910026.anemo@mba.ocn.ne.jp> <20051116184201.GJ3229@linux-mips.org>
Sender: linux-mips-bounce@linux-mips.org
>>>>> On Wed, 16 Nov 2005 18:42:01 +0000, Ralf Baechle <ralf@linux-mips.org> 
>>>>> said:
>> The CPU can surely exit from the WAIT instruction by interrupt even
>> if interrupts disabled?

ralf> That's implementation dependent behaviour, unfortunately.

I checked some MIPS32/MIPS64 datasheets and found that's really
inplementation-dependent.  The answer is YES on (perhaps) all MIPS4K?
processors but NO on 20Kc, 24K ...

And I checked x86 implemetation and found that HLT or MWAIT
instruction also must be used with interrupts enabled.  So IIUC it
seems x86 have same latency problem too.

---
Atsushi Nemoto

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