linux-mips
[Top] [All Lists]

Re: [Patch] Fix lookup_dcookie for MIPS o32

To: Ralf Baechle <ralf@linux-mips.org>
Subject: Re: [Patch] Fix lookup_dcookie for MIPS o32
From: David Daney <ddaney@avtrex.com>
Date: Wed, 19 Oct 2005 09:13:28 -0700
Cc: MIPS Linux List <linux-mips@linux-mips.org>
In-reply-to: <20051018202654.GB2659@linux-mips.org>
Original-recipient: rfc822;linux-mips@linux-mips.org
References: <17236.6951.865559.479107@dl2.hq2.avtrex.com> <20051018115155.GD2656@linux-mips.org> <43551D21.3010500@avtrex.com> <20051018202654.GB2659@linux-mips.org>
Sender: linux-mips-bounce@linux-mips.org
User-agent: Mozilla Thunderbird 1.0.7-1.1.fc3 (X11/20050929)
Ralf Baechle wrote:
On Tue, Oct 18, 2005 at 09:04:49AM -0700, David Daney wrote:


The CPU has performance counters, but they cannot trigger interrupts, so I am just using it in 'timer' mode right now. I am wondering what would happen if I added all counter samples at each clock tick. That is something I might try when I have a little free time.


Now that's truly a strange processor - what CPU are you using?


ATI Xilleon X226-A12. According to my data sheet, there are ten counters, but you can only use six at a time. They are external to the 4KEc core, and the only operations you can do to them are enable/disable counting, reset to zero and read the current values.

The counters count:
I cache hit/miss
D cache hit/miss
TLB hit/miss
JTLB hit/miss
Write merging/not merging

Perhaps I should not worry about them. Probably hooking up one of the high resolution timers would yield more useful profiling information.



I had one other problem with my cross built bash where the signal numbering of the build host was being used instead of the numbering for the target. Once I fixed bash and the lookup_dcookie system call, it seems to work flawlessly.


That bug is getting a classic.  I've fixed it in ash also - ages ago ...

I usually try to escape from the horrors of crosscompiling by using a
decent GHz MIPS system.


Yeah, In a perfect world I would have such a beast.

David Daney

<Prev in Thread] Current Thread [Next in Thread>