On Mon, 10 Oct 2005, Geert Uytterhoeven wrote:
> > It is not my code. But anyway the board has more than one discontinuous
> > io ranges(0xb4000000 is in fact for it8712 superio and legacy ios,
> So 0xb4000000 is the base for ISA and PCI I/O port accesses, right? Hence if
> mips_io_port_base is 0xb4000000, all drivers for PCI (and ISA) expansion cards
> that use inb() and friends will work.
> > it8172's system registers are located around 0xb8000000, while others
> > begins at 0xb4010000).
> So these can use ITE8172-specific access macros.
IOW, MIPS has no concept of I/O space in the CPU, so whatever is decoded
as I/O cycles to PCI/EISA/ISA is I/O and everything else is MMIO. In
particular I/O spaces are private to their respective buses -- if there
are more than one disjoint PCI/EISA/ISA buses in a given system, then each
of them can have its private 4GB or 16MB (or whatever) space reserved for
I/O cycles. If there is only one PCI/EISA/ISA bus, then mips_io_port_base
should refer to the base address where decoding as I/O cycles for that bus
starts, holding an appropriate virtual mapping, typically obtained with