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Re: [PATCH] Add support for 4KS cpu.

To: "Kevin D. Kissell" <kevink@mips.com>
Subject: Re: [PATCH] Add support for 4KS cpu.
From: Franck <vagabon.xyz@gmail.com>
Date: Tue, 4 Oct 2005 17:18:26 +0200
Cc: "Maciej W. Rozycki" <macro@linux-mips.org>, Ralf Baechle <ralf@linux-mips.org>, linux-mips@linux-mips.org
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References: <cda58cb80510040149p690397afo@mail.gmail.com> <Pine.LNX.4.61L.0510041219500.10696@blysk.ds.pg.gda.pl> <434277D5.1090603@mips.com> <Pine.LNX.4.61L.0510041358300.10696@blysk.ds.pg.gda.pl> <434289A7.50007@mips.com>
Reply-to: Franck <vagabon.xyz@gmail.com>
Sender: linux-mips-bounce@linux-mips.org
2005/10/4, Kevin D. Kissell <kevink@mips.com>:
> >  Well, the patch asked GCC to use the instruction set of the "4kec" CPU
> > for both (and also the "mips32r2" ISA, but that's overridden by the
> > former), so it must have been incorrect in the first place
>
> Which was sort-of why I replied.  In particular, the MIPS32R2 bitfield
> instructions will probably cause a reserved instruction fault on a 4KSc.
>

should I pass these options to GCC for 4KSc ?

cflags-$(CONFIG_CPU_4KSC)      += \
                       $(call set_gccflags,4kc,mips32r1,r4600,mips3,mips2) \
                       -msmartmips -Wa,--trap

Thanks
--
               Franck

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