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Re: [patch 1/5] SiByte fixes for 2.6.12

To: "Maciej W. Rozycki" <macro@linux-mips.org>
Subject: Re: [patch 1/5] SiByte fixes for 2.6.12
From: Ralf Baechle <ralf@linux-mips.org>
Date: Mon, 3 Oct 2005 13:50:16 +0100
Cc: Andrew Isaacson <adi@broadcom.com>, linux-mips@linux-mips.org
In-reply-to: <Pine.LNX.4.61L.0510031239260.8056@blysk.ds.pg.gda.pl>
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References: <20050622230042.GA17919@broadcom.com> <Pine.LNX.4.61L.0506231153080.17155@blysk.ds.pg.gda.pl> <20051001092807.GD14463@linux-mips.org> <Pine.LNX.4.61L.0510031239260.8056@blysk.ds.pg.gda.pl>
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On Mon, Oct 03, 2005 at 12:56:20PM +0100, Maciej W. Rozycki wrote:

> > >  Of course if your TLB is indeed different from that of the R4k, then you 
> > > shouldn't be setting cp0.config.mt to 1 in the first place...
> > 
> > The reason was primarily the tiny bit of extra performance because the
> > SB1 doesn't need the hazard handling overhead.  Also tlb-sb1 has a few
> 
>  That's hardly a justification for duplicating all the code; I've thought 
> the reason was actually historical -- hadn't it been simply written 
> separately initially and never got merged properly afterwards?

Historically even the R10000 had it's own copy of the TLB code - with
the sole reason of existence being it having neither hazards nor suffering
from potencial duplicate TLB entries.  Well, maybe also the very first
stages of MIPS SMP support.

Anyway, as you said that's little reason for an extra copy to exist and
so I both got axed.

> > changes that are needed to initialize a TLB in undefined state after
> > powerup.  That was needed to run Linux on firmware-less SB1 cores.
> 
>  But that's true about the power-up state of the TLB on any MIPS CPU, 
> isn't it?

Some come out of powerup with a cleared TLB but anyway, since normally
some piece of firmware takes care of these issues it's not something
Linux normally should need to worry about.

  Ralf

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