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Re: [patch 1/5] SiByte fixes for 2.6.12

To: Ralf Baechle <ralf@linux-mips.org>
Subject: Re: [patch 1/5] SiByte fixes for 2.6.12
From: "Maciej W. Rozycki" <macro@linux-mips.org>
Date: Mon, 3 Oct 2005 12:56:20 +0100 (BST)
Cc: Andrew Isaacson <adi@broadcom.com>, linux-mips@linux-mips.org
In-reply-to: <20051001092807.GD14463@linux-mips.org>
Original-recipient: rfc822;linux-mips@linux-mips.org
References: <20050622230042.GA17919@broadcom.com> <Pine.LNX.4.61L.0506231153080.17155@blysk.ds.pg.gda.pl> <20051001092807.GD14463@linux-mips.org>
Sender: linux-mips-bounce@linux-mips.org
On Sat, 1 Oct 2005, Ralf Baechle wrote:

> >  Of course if your TLB is indeed different from that of the R4k, then you 
> > shouldn't be setting cp0.config.mt to 1 in the first place...
> 
> The reason was primarily the tiny bit of extra performance because the
> SB1 doesn't need the hazard handling overhead.  Also tlb-sb1 has a few

 That's hardly a justification for duplicating all the code; I've thought 
the reason was actually historical -- hadn't it been simply written 
separately initially and never got merged properly afterwards?

> changes that are needed to initialize a TLB in undefined state after
> powerup.  That was needed to run Linux on firmware-less SB1 cores.

 But that's true about the power-up state of the TLB on any MIPS CPU, 
isn't it?

  Maciej

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