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Re: Performance bug in c-r4k.c cache handling code

To: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Subject: Re: Performance bug in c-r4k.c cache handling code
From: Thiemo Seufer <ths@networkno.de>
Date: Mon, 19 Sep 2005 20:31:18 +0200
Cc: linux-mips@linux-mips.org
In-reply-to: <20050920.015424.41632255.anemo@mba.ocn.ne.jp>
Original-recipient: rfc822;linux-mips@linux-mips.org
References: <20050919154056.GG3386@hattusa.textio> <20050920.015424.41632255.anemo@mba.ocn.ne.jp>
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Atsushi Nemoto wrote:
> >>>>> On Mon, 19 Sep 2005 17:40:56 +0200, Thiemo Seufer <ths@networkno.de> 
> >>>>> said:
> 
> ths> I found an performance bug in c-r4k.c:r4k_dma_cache_inv, where a
> ths> Hit_Writeback_Inv instead of Hit_Invalidate is done. Ralf
> ths> mentioned this is probably due to broken Hit_Invalidate cache ops
> ths> on some CPUs, does anybody have more information about this? The
> ths> appended patch works apparently fine on R4400, R4600v2.0, R5000.
> 
> Just a question: Are there any performance advantage of using
> Hit_Invalidate instead of Hit_Writeback_Inv if the target line was
> CLEAN?

I wouldn't think so, but it depends on the particular implementation.


Thiemo

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