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Re: Performance bug in c-r4k.c cache handling code

To: ths@networkno.de
Subject: Re: Performance bug in c-r4k.c cache handling code
From: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Date: Tue, 20 Sep 2005 01:54:24 +0900 (JST)
Cc: linux-mips@linux-mips.org
In-reply-to: <20050919154056.GG3386@hattusa.textio>
Original-recipient: rfc822;linux-mips@linux-mips.org
References: <20050919154056.GG3386@hattusa.textio>
Sender: linux-mips-bounce@linux-mips.org
>>>>> On Mon, 19 Sep 2005 17:40:56 +0200, Thiemo Seufer <ths@networkno.de> said:

ths> I found an performance bug in c-r4k.c:r4k_dma_cache_inv, where a
ths> Hit_Writeback_Inv instead of Hit_Invalidate is done. Ralf
ths> mentioned this is probably due to broken Hit_Invalidate cache ops
ths> on some CPUs, does anybody have more information about this? The
ths> appended patch works apparently fine on R4400, R4600v2.0, R5000.

Just a question: Are there any performance advantage of using
Hit_Invalidate instead of Hit_Writeback_Inv if the target line was
CLEAN?

---
Atsushi Nemoto

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