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handler_tlb[lsm] not flushed explicitly

To: linux-mips@linux-mips.org, ralf@linux-mips.org
Subject: handler_tlb[lsm] not flushed explicitly
From: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Date: Mon, 12 Sep 2005 11:36:17 +0900 (JST)
In-reply-to: <20050715152329Z8226727-3678+3178@linux-mips.org>
Organization: TOSHIBA Personal Computer System Corporation
Original-recipient: rfc822;linux-mips@linux-mips.org
References: <20050715152329Z8226727-3678+3178@linux-mips.org>
Sender: linux-mips-bounce@linux-mips.org
>>>>> On Fri, 15 Jul 2005 16:23:23 +0100, ralf@linux-mips.org said:
ralf> Modified files:
ralf>   arch/mips/mm   : c-r4k.c c-tx39.c pg-r4k.c tlbex.c 

ralf> Log message:
ralf>   Avoid SMP cacheflushes.  This is a minor optimization of startup but
ralf>   will also avoid smp_call_function from doing stupid things when called
ralf>   from a CPU that is not yet marked online.

This change removed some flush_icache_range() from tlbex.c.  Now the
refill handler is flushed by last flush_icache_range() in trap_init(),
but it seems handle_tlbl[], handle_tlbs[], handle_tlbm[] are not
explicitly flushed to main memory.

We should call __flush_cache_all() instead of flush_icache_range() in
 trap_init() ?

---
Atsushi Nemoto

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