| To: | David Daney <ddaney@avtrex.com> |
|---|---|
| Subject: | RE: Problems with Intel e100 driver on new MIPS port, was: Advice needed WRT very slow nfs in new port... |
| From: | "Maciej W. Rozycki" <macro@linux-mips.org> |
| Date: | Fri, 1 Jul 2005 09:57:37 +0100 (BST) |
| Cc: | Michael Stickel <michael@cubic.org>, linux-mips@linux-mips.org |
| In-reply-to: | <01049E563C8ECC43AD6B53A5AF419B38098BD1@avtrex-server2.hq2.avtrex.com> |
| Original-recipient: | rfc822;linux-mips@linux-mips.org |
| References: | <01049E563C8ECC43AD6B53A5AF419B38098BD1@avtrex-server2.hq2.avtrex.com> |
| Sender: | linux-mips-bounce@linux-mips.org |
On Thu, 30 Jun 2005, David Daney wrote: > It seems that it is a memory consistancy problem of some sort. By > placing wbflush() after all writes to NIC registers it works. This > leads me to think that either the driver is buggy WRT processors that > have write-back queues or my implementation (the default implementation) > of writeb() and friends is buggy on this processor. Now it could be > that all that is needed is wmb() before some of the register writes, but > since on my processor they both do the same thing (sync) it is hard to > tell. Most likely that code has only been ever used on i386 systems (who'd want to use such a weird Ethernet chip elsewhere?), so don't expect it to be terribly sane. Maciej |
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