| To: | Michael Stickel <michael@cubic.org> |
|---|---|
| Subject: | Re: Problems with Intel e100 driver on new MIPS port, was: Advice needed WRT very slow nfs in new port... |
| From: | David Daney <ddaney@avtrex.com> |
| Date: | Thu, 30 Jun 2005 11:23:29 -0700 |
| Cc: | linux-mips@linux-mips.org |
| In-reply-to: | <42C39066.2060406@cubic.org> |
| Original-recipient: | rfc822;linux-mips@linux-mips.org |
| References: | <42C34C4D.9020902@avtrex.com> <20050629.195743.48512936.imp@bsdimp.com> <42C359F8.4060000@avtrex.com> <20050629.204246.102671266.imp@bsdimp.com> <42C39066.2060406@cubic.org> |
| Sender: | linux-mips-bounce@linux-mips.org |
| User-agent: | Mozilla Thunderbird 1.0.2-6 (X11/20050513) |
Michael Stickel wrote: M. Warner Losh wrote:Add some debugging to the interrupt routine of the e100 and see what happens.In message: <42C359F8.4060000@avtrex.com> David Daney <ddaney@avtrex.com> writes: : M. Warner Losh wrote: : > In message: <42C34C4D.9020902@avtrex.com> : > David Daney <ddaney@avtrex.com> writes: : > : Does anyone have any idea what would cause 1000mS delay?: > : > That's remarkably close to 1s. This often indicates that the transmit: > of your next packet is causing the receive buffer to empty. This is : > usually due to blocked interrupts, or a failure to enable interrupts.: > : : But I observe ever increasing counts for the device in /proc/interrupts. : So the interrupts are working somewhat.Are you sure that you've routed the interrupts correctly? Maybe those interrupts are 'really' for a different device.... The interrupt routine is getting called each time a packet is received.It looks like packets are not being transmitted until the interrupt for the the received packet is received. If I ping the board at different intervals the round trip time is always almost exactly equal to the ping interval. So if I ping every 50mS the round trip time is 50mS, ping every 200mS gives a RTT of 200mS, etc. Any more ideas?I am thinking that perhaps the CPU write-back-queue is interfearing with writes to the NIC's registers. Perhaps I will try to disable it. David Daney. |
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