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[patch 4/5] SiByte fixes for 2.6.12

To: linux-mips@linux-mips.org
Subject: [patch 4/5] SiByte fixes for 2.6.12
From: "Andrew Isaacson" <adi@broadcom.com>
Date: Wed, 22 Jun 2005 16:01:51 -0700
In-reply-to: <20050622230003.GA17725@broadcom.com>
Original-recipient: rfc822;linux-mips@linux-mips.org
Sender: linux-mips-bounce@linux-mips.org
User-agent: Mutt/1.4.2.1i
If the CPU Options get out of sync with the CONFIG_CPU_ options,
cpu_cache_init() can end up being a noop.  Stop with a useful message
in that case rather than running on without cache functions.

Signed-Off-By: Andrew Isaacson <adi@broadcom.com>

Index: linux-2.6-work/arch/mips/mm/cache.c
===================================================================
--- linux-2.6-work.orig/arch/mips/mm/cache.c    2005-06-22 11:17:20.000000000 
-0700
+++ linux-2.6-work/arch/mips/mm/cache.c 2005-06-22 11:17:32.000000000 -0700
@@ -122,6 +122,8 @@
     defined(CONFIG_CPU_MIPS64) || defined(CONFIG_CPU_TX49XX) || \
     defined(CONFIG_CPU_RM7000) || defined(CONFIG_CPU_RM9000)
                ld_mmu_r4xx0();
+#else
+               panic("Unknown CPU with r4k TLB");
 #endif
        } else switch (current_cpu_data.cputype) {
 #ifdef CONFIG_CPU_R3000

--



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