| To: | linux-mips@linux-mips.org |
|---|---|
| Subject: | [patch 1/5] SiByte fixes for 2.6.12 |
| From: | "Andrew Isaacson" <adi@broadcom.com> |
| Date: | Wed, 22 Jun 2005 16:00:42 -0700 |
| In-reply-to: | <20050622230003.GA17725@broadcom.com> |
| Original-recipient: | rfc822;linux-mips@linux-mips.org |
| Sender: | linux-mips-bounce@linux-mips.org |
| User-agent: | Mutt/1.4.2.1i |
SB1 does not use the R4K TLB code.
Signed-Off-By: Andrew Isaacson <adi@broadcom.com>
Index: linux-2.6-work/arch/mips/kernel/cpu-probe.c
===================================================================
--- linux-2.6-work.orig/arch/mips/kernel/cpu-probe.c 2005-06-22
11:17:22.000000000 -0700
+++ linux-2.6-work/arch/mips/kernel/cpu-probe.c 2005-06-22 11:17:29.000000000
-0700
@@ -583,6 +583,8 @@
switch (c->processor_id & 0xff00) {
case PRID_IMP_SB1:
c->cputype = CPU_SB1;
+ c->options &= ~MIPS_CPU_4KTLB;
+ c->options |= MIPS_CPU_TLB;
#ifdef CONFIG_SB1_PASS_1_WORKAROUNDS
/* FPU in pass1 is known to have issues. */
c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
--
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