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tlb magic

To: linux-mips@linux-mips.org
Subject: tlb magic
From: "Mad Props" <madprops@gmx.net>
Date: Mon, 13 Jun 2005 16:06:34 +0200 (MEST)
Original-recipient: rfc822;linux-mips@linux-mips.org
Sender: linux-mips-bounce@linux-mips.org
Hi,

I'm trying to understand how to implement an TLB Exception handler for a
MIPS32 ( 4KC ). As far as I got it, it makes sense to locate the user
process page tables in kseg2 to save physical memory. The book I'm reading
states another advantage using kseg2. I'm not quite sure what they mean,
stating that

"It provides an easy mechanism for remapping a new user page table when
changing context, without having to find enough virtual addresses in the OS
to map all the page tables at once. Instead, you just change the ASID value,
and the kseg2 pointer to the page table is now automatically remapped onto
the correct page table. It's nearly magic."


1. Is there only one kseg2 containing all page tables for 256 processes,
i.e. only one ASID is used or

2. Has each page table it's own address space ( using different ASID for
those addresses in kseg2 )

3. Will I need another untranslated page table in kseg0/kseg1 to translate
kseg2 addresses ?

4. What is this kseg2 pointer they are talking about ?

5. Are they talking about the ASID in EntryHi ?

6. Where is the magic ?

Would be smashing if anybody could help me out.

Kind regards,

Thomas

 

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